The ARM Cortex-A8 processor is the most advanced, high performance, low-power processor by ARM. Based on the ARMv7 architecture, the processor suits a variety of mobile and consumer applications, including mobile phones, STBs, game consoles and car navigation. As the core technology of Cortex-A8 processor,
NEON technology has the flexibility to implement multiple combinations of video encode/decode, 3D graphics, speech processing, audio decoding, image processing and baseband processing.
NEON technology is a 64,128bit single instruction multiple data stream (SIMD) instruction set. NEON supports 8-, 16-, 32-, 64bit integer and single precision floating- point SIMD operations to handle audio, video, image and other data processing. NEON technology has separate registers and pipeline, which is independent of the ARM integer pipeline.
Through the use of NEON technology's multimedia features, Cortex-A8 processor can decode MPEG4 VGA video (including the de-blocking filter, YUV to RGB conversion and other operations) at 275MHz with 30fps speed. NEON technology can execute an MP3 decoder with processor frequency lower than 10MHz.
Cortex-A8 NEON basics
The Cortex-A8 processor's NEON media processing engine pipeline starts at the end of the main integer pipeline. As a result, all exceptions and branch mispredictions are resolved before instructions reach it. More importantly, there is a zero load-use penalty for data in the Level-1 cache.
The ARM integer unit generates the addresses for NEON loads and stores as they pass through the pipeline, thus allowing data to be fetched from the Level-1 cache before it is required by a NEON data processing operation.
Deep instruction and load-data buffering between the NEON engine, the ARM integer unit and the memory system allow the latency of Level-2 accesses to be hidden for streamed data. A store buffer prevents NEON stores from blocking the pipeline and detects address collisions with the ARM integer unit accesses and NEON loads.
The NEON unit is decoupled from the main ARM integer pipeline by the NEON instruction queue (NIQ). The ARM Instruction Execute Unit can issue up to two valid instructions to the NEON unit each clock cycle. NEON has 128bit wide load and store paths to the Level-1 and Level-2 cache, and supports streaming from both.
The NEON engine has its own 10 stage pipeline that begins at the end ARM integer pipeline. Since all mispredicts and exceptions have been resolved in the ARM integer unit, once an instruction has been issued to the NEON engine it must be completed as it cannot generate exceptions. NEON instructions are issued and retired in-order. A data processing instruction is either a NEON integer instruction or a NEON floating-point instruction.
The Cortex-A8 NEON unit does not parallel issue two data-processing instructions to avoid the area overhead with duplicating the data-processing functional blocks, and to avoid timing critical paths and complexity overhead associated with the muxing of the read and write register ports.
The NEON integer data path consists of three pipelines: an integer multiply/accumulate pipeline (MAC), an integer Shift pipeline and an integer ALU pipeline. A load-store/permute pipeline is responsible for all NEON load/stores, data transfers to/from the integer unit, and data permute operations such as interleave and de-interleave. The NEON floating-point (NFP) data path has two main pipelines: a multiply pipeline and an add pipeline.
