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There are several aspects of audio converter design that are generally not well understood but have a dramatic impact on performance, both measurable and audible. Audio converter IC manufacturers generally give circuit recommendations to address these issues but rarely discuss the reasoning behind these suggestions, how performance is affected and why it is important to follow the rules.
However, once a designer has an insight into the issues, it is possible to identify the compromises that often exist in the manufacturers recommendations. This can lead to intelligent insights to lower cost, or in some instances, improve performance.
One of these areas is interfacing to the sampling networks of analog-to-digital-converters. Today's high-performance A/D converters are based on highly oversampled multi-bit delta-sigma conversion with sampling circuits that operate at frequencies several orders of magnitude beyond the audio range. An understanding of how to properly interface to these networks is probably the least understood topic in A/D systems design and remains one of the "magical" areas of audio circuit design.
A/D converter sampling circuits
A simplified sampling network is shown in Figure 1. The operation of the network can be broken down into two phases. During the initial phase or the capture phase, switch one (SW1) is closed and switch two (SW2) is open. This allows the sampling capacitor (CIN) to charge to the voltage presented by the external analog drivers. During the second phase, SW1 is open and SW2 is closed which allows the captured charge on CIN to be transferred to the integrator as a voltage for conversion.
Figure 1. Simplified A/D sampling circuit.
The repetition rate of this process is determined by the frequency of the oversampling clock and is typically 128 times the output sample rates from 16 to 50 kHz which equates to a 6.144-MHz analog sample rate for a 48-kHz output sample rate. Understanding and properly addressing the challenges presented by the high speed sampling and switching is very important to a successful design.
A representative input current waveform is shown in Figure 2. The polarity and total charge transferred within each period is a function of the input signal amplitude, signal polarity, sampling frequency and the capacitance of the sampling capacitor. This high-speed switching, and the transient currents they create, presents an impossible load for the majority of operational amplifiers.
Figure 2. A/D input sampling currents.
Consider that during the initial capture phase, the buffer amplifier is required to drive a discharged capacitor that essentially appears to be an instantaneous short circuit to Vbias. Conversely, during the conversion phase the sampling capacitor is disconnected from the buffer and the load becomes an open circuit. This process is repeated at the oversampling rate and the external buffer amplifier typically has problems with the transient load conditions when driving the sampling capacitor directly. It is rather obvious that requirements demanded by the switched capacitor loading are not typical of standard audio circuitry.
In addition to the linear sampling currents, there are several sources of nonlinear signal level dependent sampling currents within the sampling networks. Since this nonlinear current must be supplied by the signal source, this will translate to distortion if the source impedance is sufficiently large. The magnitude of this nonlinear current will vary between different converter designs and architectures and converter manufacturers generally recommend driver source resistance to be less than 100 Ω, and in many cases much less, to meet stated distortion specifications.
The analog sections of audio A/D converters typically operate with a single 5- or 3.3-V power supply and, as a result, the input signal must be biased at a DC voltage near mid-supply. This is shown in Figure 1 where the sampling capacitor is connected to the internal bias voltage, Vbias. Differences in the quiescent voltage of the external buffer and the internal bias voltage translate to non-symmetrical currents between equal magnitude positive and negative analog signal inputs. This can have a negative impact on distortion performance and creates non-symmetrical clipping behavior.
The best remedy is to take advantage of the internally generated bias voltage that is typically available on one of the device pins. The intended purpose of this output is to provide an external capacitor to filter noise from the bias voltage. However, this pin may also be used to bias the input buffer circuits, but a word of caution. These outputs are generally not intended to supply a significant amount of current and often must be buffered prior to biasing the input circuitry. Examples of this technique are often listed in the applications sections of converter data sheets.
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